Low Power Design Methodologies

Today's designs are getting faster and more complex, allowing designers the freedom to innovate in new ways. However, innovation brings with it challenges and uncertainty. The issue becomes how to design something more complex quickly and with high quality in a constantly evolving semiconductor design automation tools.

The continual increase of chip size and decrease of process feature size are making timing closre more and more challenging. With Very Deep Sub MIcron processes (90nm and below), new challenges due to increasing wire delays and On-Chip Process variations in both low power design methodologies and timing closure. Learn more about these strategies from a recent publication for SiliconPro in ICICDT conference.