ASIC Emulation and Prototyping

Because of the increasing complexity and size of ASIC and SoC designs, the verification became one of the most challenging tasks in most ASIC projects. Not only is it becoming more and more difficult to detect bugs in today's large ASIC designs, but also the performance of simulators decreases rapidly to a point where the task and functional verification and software testing would take many man years to complete. Many designers have turned into emulation and prototyping solutions as a way to increase the simulation performance (speed) and at the same time improve verification efficiency with the ability to do real software/hardware integration and debugging. In addition, technology scaling has brought current manufacturing processes to the sub 100nm region. The behaviour of the IC devices and the interconnect sytems in nanometer technologies bring new physical effects that, in addition to traditional well known failure modes, open new challenges in IC yields. With the increasing complexity of ASIC designs, logic debuggon on silicon becomes difficult because of the limited ability to observe the chip's interior states.