The SP3000 AWGN core generates white Gaussian noise generator, which can be used to perform BER to extremely low BER levels (~10-15). The SP3000 uses a combination of the Box-Muller algorithm and the central limit theorem. The Box-Muller algorithm generates a unit normal random variable via a transformation of two independent random variables that are uniformly distributed. The outputs of multiple parallel Box-Muller designs are then averaged to obtain a PDF that is Gaussian to up to 10σ.
The Additive White Gaussian Noise (AWGN) generator is widely used in BERT curve calculation for Forward Error Correction (FEC) IPs. The software-based AWGN generator can take several days or several weeks for the BER curve calculation when reach low bit error rates. Also, the transferring software generated noise sample to the hardware IP is highly inefficient and it can be a performance bottleneck.
Hardware-based AWGN noise generator offers the speed of BER by several orders of magnitude. It can be connected to the designed IP for BERT curve calculation in the simulation. And also, it can be synthesized and implemented in FPGA with designed IP. In this case, the design IP can be tested in FPGA just like the prototype tested in the lab.
We tested the hardware noise generator core using the iScope. Testing included two phases, in phase1 the noise generator run freely and the generated data is collected periodically in the iScope readMem. The resulting histogram is shown overlaying the expected Gaussian distribution (log scale is used).
In phase2, only samples > 5σ were written the the iScope readMem, this way the test was speeded up over million times to test the tail end of the noise distribution (log scale is used).